library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;

-- synopsys translate_off
-- synthesis translate_off
--library csx_HRDLIB_FTSM;
-- use csx_HRDLIB_FTSM.VCOMPONENTS.all;
-- synthesis translate_on
-- synopsys translate_on


library work;
 use work.router_pack.all;


--- This entity was generated basing on Petrify Result: --


-------------------------------------------------------------------------------
entity delay_line is
-------------------------------------------------------------------------------
generic(
   num_of_buffers : integer := 1 -- minimal number is 1
);
port( 
      DI  : in   std_logic;   
      DO  : out  std_logic   
);           
-------------------------------------------------------------------------------
end delay_line ;
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
architecture delay_line_arch of delay_line is
-------------------------------------------------------------------------------
	COMPONENT dl01d1  -- buffer 1x
	PORT(
	  i : IN  std_logic;
	  z : OUT std_logic
	);
	END COMPONENT;

signal del_line  : std_logic_vector(num_of_buffers downto 0);

begin

del_line(0) <= DI;
DO          <= del_line(num_of_buffers) ;


del_line_gen: for i in 0 to (num_of_buffers-1) generate

 u_del_line_dl01d1: dl01d1                           
  port map(
      i   => del_line(i),  
      z   => del_line(i+1)
 );

end generate;

-------------------------------------------------------------------------------
end delay_line_arch;
-------------------------------------------------------------------------------                 

   
-------------------------------------------------------------------------------
configuration  delay_line_cfg  of delay_line is
-------------------------------------------------------------------------------
   for delay_line_arch
   end for;
-------------------------------------------------------------------------------
end  delay_line_cfg;              
-------------------------------------------------------------------------------
                 
